摘要:
囿于材料和工艺稳定性等原因，纳米级集成电路制造依然基于193 nm激发光的工艺，光刻波长远大于版图尺寸，使得制造中光的干涉和衍射现象极大降低了分辨率，影响了芯片质量，因此版图在制造前需要使用可制造性模型进行查错。传统模型对制造过程进行物理建模，通过对模型中的矩阵进行分解得到卷积核，所使用的物理模型不仅复杂，而且应用难度高，加之还有物理模型缺失的情况，因此难以描述具有上千参数的生产线。本文使用卷积的形式作为可制造性模型的框架，通过优化算法提取版图到硅片轮廓这一过程的信息并以卷积核的形式体现出来，卷积核中的每一个元素均为根据已知的生产线输入输出数据优化得出，是描述制造过程的一个维度。该模型克服了传统模型需要工艺参数等机密信息的缺陷，同时具有更强的描述制造过程的能力；模型甚至可以包含版图校正信息，描述从版图到硅片轮廓这一全流程。该模型在65 nm工艺下的实验结果表明该模型具有8 nm的精度。
Abstract:
Limited by materials and process stability, the nano-scale IC manufacturing process is still based on the 193 nm light technology and the wavelength is larger than the feature size of layout, thus the induced interference and diffraction greatly reduce the resolution, which affect the quality of the chip. So the layout needs to be checked by the design-for-manufacturability (DfM) model before manufacturing. Traditional DfM models describe the process steps using physical models, and deduce the convolution kernels by decomposing the matrix in corresponding physical models, which are not only complicated but also hard to use; thus combined with the insu?ciency of physical models, it is di?cult to describe the process with thousands of parameters. This paper uses convolution form as the framework of DfM model, and deduces the relationship, represented as convolution kernels, between layout and contour by an optimization method. Every element in the convolution kernels is optimized based on the input and output data of the process and is also a dimension to describe the process. This model overcomes the disadvantages of the traditional model which needs confidential information such as process parameters, and it has more powerful capability to describe the process. Moreover, the model can contain the layout correction information, and describe the process from layout to contour. Experiment results for 65 nm process show that the model has an accuracy of 8 nm.
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