摘要:
基于蒙特卡罗方法研究空间高能离子在65—32 nm绝缘体上硅静态随机存取存储器(SOI SRAM)中产生的灵敏区沉积能量谱、单粒子翻转截面和空间错误率特性及内在的物理机理.结果表明:单核能为200 MeV/n的空间离子在60—40 nm厚的灵敏区中产生的能损歧离导致纳米级SOI SRAM在亚线性能量转移阈值区域出现单粒子翻转;宽的二次电子分布导致灵敏区仅能部分收集单个高能离子径迹中的电子-空穴对,致使灵敏区最大和平均沉积能量各下降25%和33.3%,进而引起单粒子翻转概率降低,以及在轨错误率下降约80%.发现俘获带质子直接电离作用导致65 nm SOI SRAM的在轨错误率增大一到两个数量级.
Abstract:
Based on Monte-Carlo method, the characteristics and physical mechanisms for deposited-energy spectra in sensitive volume (SV), single event upset cross sections, and on-orbit error rates in 65–32 nm silicon-on-insulator static random access memory (SOI SRAM) devices induced by space energetic ions are investigated. Space ions on geostationary earth orbit exhibit a flux peak at an energy point of about 200 MeV/n. In consequence, the single event response of nanometric SOI SRAMs under 200 MeV/n heavy ions is studied in detail. The results show that 200 MeV/n space ions exhibit the large straggling of deposited-energy in the device SV with thickness ranging from 60 nm to 40 nm, which causes the single event upsets to occur in the sub-LETth region. The device SV can only partially collect the electron-hole pairs in the single ion track with a wide distribution of secondary electrons. As a result, the maximum and average deposited-energy in the SV decrease by 25%and 33.3%, respectively. Further, the single event upset probability decreases and the on-orbit error rate decreases by about 80%. With the downscaling of feature size, the per-bit saturated cross sections and on-orbit error rates of nanometric SOI SRAM devices decrease dramatically. The phenomenon of constant-increasing single event upset cross section with higher ion linear energy transfer (LET) is not observed, owing to the fact that (a) the density of electron-hole pairs in the track of 200 MeV/n space ion is relatively low and (b) the SOI device has thin sensitive volume, which results in the fact that the secondary-electron effect cannot upset nearby sensitive cells. Besides, it is found that the direct-ionization process of trapped protons leads to an increase of on-orbit error rate of 65 nm SOI SRAM by one to two orders of magnitude.