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Figure 1.  ALD Al₂O₃ stacked on nitride SiO₂. (a) Schematic process of the MOS capacitors poly-Si/Al₂O₃/SiO₂/SiC/Ni. (b) Transmission electron microscopy (TEM) image of the prepared MOS stack. (c) Schematic illustration of the MOS sample measurement by XPS. XPS spectrum for the MOS stack: (d) XPS carried on the Al₂O₃, SiO₂ and SiC films for special positions at O 1s, Si 2p and Al 2p; (e) XPS carried on the cross depth of SiO₂ films by controlling plasma etching time from 10 s to 40 s at N 1s binding position.

Figure 2.  Interfacial state defects and dielectric breakdown characteristics of pure SiO₂ and Al₂O₃ dielectric MOS capacitors. (a) HF C–V curves of MOS capacitors. (b) Room temperature (300 K) results of current density (J)–electric field (E) plots of MOS capacitors. A Fowler–Nordheim plot for pure (c) Al₂O₃ and (d) SiO₂ dielectric MOS capacitors.

Figure 3.  Interfacial characteristics for the stack Al₂O₃ dielectric samples grown by different thicknesses SiO₂. (a)–(c) HF C–V curves of MOS capacitors for different thicknesses SiO₂. (d) Density of interface states (D_it) as a function of energy from the SiC conduction band edge, extracted from C–V analysis at room temperatures for the stack Al₂O₃ dielectric samples grown by different thicknesses SiO₂. (e)–(h) HF C–V curves of MOS capacitors with increasing annealing time. (i) Density of interface states with increasing annealing time of the SiO₂ samples. (j) The density of interfacial states changes with increasing annealing time of the SiO₂ samples.

Figure 4.  Dielectric breakdown characteristics of the stack Al₂O₃ dielectric samples grown by different thicknesses SiO₂. (a) Room temperature (300 K) results of current density (J)–electric field (E) plots of MOS capacitors. (b) A Fowler–Nordheim plot for MOS capacitors. (c) Schematic band offset of the MOS capacitors Ni/SiC/SiO₂/Al₂O₃/poly-Si. (d) Saturation thickness of stacked SiO₂ in atomic-layer-deposited Al₂O₃ gate on 4HSiC.